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1 of 12 022301 features integrated nv sram, real time clock, crystal, power-fail control circuit and lithium energy source clock registers are accessed identical to the static ram. these registers are resident in the eight top ram locations century byte register totally nonvolatile with over 10 years of operation in the absence of power bcd coded century, year, month, date, day, hours, minutes, and seconds with automatic leap year compensation valid up to the year 2100 battery voltage level indicator flag power-fail write protection allows for 10% v cc power supply tolerance lithium energy source is electrically disconnected to retain freshness until power is applied for the first time standard jedec bytewide 2k x 8 static ram pinout quartz accuracy 1 minute a month @ 25 c, factory calibrated pin assignment pin description a0-a10 - address inputs ce - chip enable oe - output enable we - write enable v cc - power supply input gnd - ground dq0-dq7 - data input/outputs ordering information ds1742-xxx (5v) -70 70 ns access -100 100 ns access ds1742w-xxx (3.3v) -120 120 ns access -150 150 ns access description the ds1742 is a full function, year 2000-compliant (y2kc), real-time clock/calendar (rtc) and 2k x 8 non-volatile static ram. user access to all registers within the ds1742 is accomplished with a bytewide interface as shown in figure 1. the real time clock (rtc) information and control bits reside in the eight uppermost ram locations. the rtc registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour bcd format. corrections for the day of the month and leap year are made automatically. ds1742 y2kc nonvolatile timekeeping ram www.dalsemi.com v cc a 8 a 9 we oe a 10 ce dq7 dq6 dq5 dq4 dq3 1 2 3 4 5 6 7 8 9 10 11 12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 gnd 24 23 22 21 20 19 18 17 16 15 14 13
ds1742 2 of 12 the rtc clock registers are double-buffered to avoid access of incorrect data that can occur during clock update cycles. the double buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. the ds1742 also contains its own power-fail circuitry, which deselects the device when the v cc supply is in an out of tolerance condition. this feature prevents loss of data from unpredictable system operation brought on by low v cc as errant access and update cycles are avoided. clock operations-reading the clock while the double-buffered register structure reduces the chance of reading incorrect data, internal updates to the ds1742 clock registers should be halted before clock data is read to prevent reading of data in transition. however, halting the internal clock register updating process does not affect clock accuracy. updating is halted when a 1 is written into the read bit, bit 6 of the century register, see table 2. as long as a 1 remains in that position, updating is halted. after a halt is issued, the registers reflect the count, that is day, date, and time that was current at the moment the halt command was issued. however, the internal clock registers of the double-buffered system continue to update so that the clock accuracy is not affected by the access of data. all of the ds1742 registers are updated simultaneously after the internal clock register updating process has been re-enabled. updating is within a second after the read bit is written to 0. the read bit must be a zero for a minimum of 500 s to ensure the external registers will be updated. ds1742 block diagram figure 1 ds1742 truth table table 1 v cc ce oe we mode dq power v ih x x deselect high-z standby v il xv il write data in active v il v il v ih read data out active v cc >v pf v il v ih v ih read high-z active v so ds1742 3 of 12 stopping and starting the clock oscillator the clock oscillator may be stopped at any time. to increase the shelf life, the oscillator can be turned off to minimize current drain from the battery. the osc bit is the msb (bit 7) of the seconds registers, see table 2. setting it to a 1 stops the oscillator. frequency test bit as shown in table 2, bit 6 of the day byte is the frequency test bit. when the frequency test bit is set to logic 1 and the oscillator is running, the lsb of the seconds register will toggle at 512 hz. when the seconds register is being read, the dq0 line will toggle at the 512 hz frequency as long as conditions for access remain valid (i.e., ce low, oe low, we high, and address for seconds register remain valid and stable). clock accuracy the ds1742 is guaranteed to keep time accuracy to within 1 minute per month at 25 c. the rtc is calibrated at the factory by dallas semiconductor using nonvolatile tuning elements. the ds1742 does not require additional calibration. for this reason, methods of field clock calibration are not available and not necessary. clock accuracy is also effected by the electrical environment and caution should be taken to place the rtc in the lowest level emi section of the pcb layout. for additional information please see application note 58. ds1742 register map table 2 data address b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 function/range 7ff 10 year year year 00-99 7fe x x x 10 mo month month 01-12 7fd x x 10 date date date 01-31 7fc bf ft x x x day day 01-07 7fb x x 10 hour hour hour 00-23 7fa x 10 minutes minutes minutes 00-59 7f9 osc 10 seconds seconds seconds 00-59 7f8 w r 10 century century control 00-39 osc = stop bit r = read bit ft = frequency test w = write bit x = see note below bf = battery flag note: all indicated ?x? bits are not dedicated to any particular function and can be used as normal ram bits. retrieving data from ram or clock the ds1742 is in the read mode whenever oe (output enable) is low, we (write enable) is high, and ce (chip enable) is low. the device architecture allows ripplethrough access to any of the address locations in the nv sram. valid data will be available at the dq pins within t aa after the last address input is stable, providing that the ce , and oe access times and states are satisfied. if ce , or oe access times and states are not met, valid data will be available at the latter of chip enable access (t cea ) or at output enable access time (t oea ). the state of the data input/output pins (dq) is controlled by ce , and oe . if the outputs are activated before t aa , the data lines are driven to an intermediate state until t aa . if the
ds1742 4 of 12 address inputs are changed while ce , and oe remain valid, output data will remain valid for output data hold time (t oh ) but will then go indeterminate until the next address access. writing data to ram or clock the ds1742 is in the write mode whenever we , and ce are in their active state. the start of a write is referenced to the latter occurring transition of we , on ce . the addresses must be held valid throughout the cycle. ce , or we must return inactive for a minimum of t wr prior to the initiation of another read or write cycle. data in must be valid t ds prior to the end of write and remain valid for t dh afterward. in a typical application, the oe signal will be high during a write cycle. however, oe can be active provided that care is taken with the data bus to avoid bus contention. if oe is low prior to we transitioning low the data bus can become active with read data defined by the address inputs. a low transition on we will then disable the outputs t wez after we goes active. data retention mode the 5-volt device is fully accessible and data can be written or read only when v cc is greater than v pf . however, when v cc is below the power fail point, v pf , (point at which write protection occurs) the internal clock registers and sram are blocked from any access. when v cc falls below the battery switch point v so (battery supply level), device power is switched from the v cc pin to the backup battery. rtc operation and sram data are maintained from the battery until v cc is returned to nominal levels. the 3.3 volt device is fully accessible and data can be written or read only when v cc is greater than v pf . when v cc falls below the power fail point, v pf , access to the device is inhibited. if v pf is less than vso , the device power is switched from v cc to the backup supply (v bat ) when v cc drops below v pf . if v pf is greater than vso , the device power is switched from v cc to the backup supply (v bat ) when v cc drops below vso . rtc operation and sram data are maintained from the battery until v cc is returned to nominal levels. battery longevity the ds1742 has a lithium power source that is designed to provide energy for clock activity, and clock and ram data retention when the v cc supply is not present. the capability of this internal power supply is sufficient to power the ds1742 continuously for the life of the equipment in which it is installed. for specification purposes, the life expectancy is 10 years at 25 c with the internal clock oscillator running in the absence of v cc power. each ds1742 is shipped from dallas semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. when v cc is first applied at a level greater than v pf , the lithium energy source is enabled for battery backup operation. actual life expectancy of the ds1742 will be much longer than 10 years since no lithium battery energy is consumed when v cc is present. battery monitor the ds1742 constantly monitors the battery voltage of the internal battery. the battery flag bit (bit 7) of the day register is used to indicate the voltage level range of the battery. this bit is not writable and should always be a 1 when read. if a 0 is ever present, an exhausted lithium energy source is indicated and both the contents of the rtc and ram are questionable.
ds1742 5 of 12 absolute maximum ratings* voltage on any pin relative to ground -0.3v to +6.0v operating temperature 0 c to 70 c storage temperature -40 c to +85 c soldering temperature see j-std-020a specification (see note 7) * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. operating range range temperature v cc commercial 0c to +70c 3.3v 10% or 5v 10% recommended dc operating conditions (over the operating range) parameter symbol min typ max units notes logic 1 voltage all inputs v cc = 5v 10% v ih 2.2 v cc +0.3v v 1 v cc = 3.3v 10% v ih 2.0 v cc +0.3v v 1 logic 0 voltage all inputs v cc = 5v 10% v il -0.3 0.8 v 1 v cc = 3.3v 10% v il -0.3 0.6 v 1 dc electrical characteristics (over the operating range; v cc = 5.0v 10%) parameter symbol min typ max units notes active supply current i cc 15 50 ma 2, 3 ttl standby current ( ce =v ih ) i cc1 1 3 ma 2, 3 cmos standby current ( ce = v cc - 0.2v) i cc2 1 3 ma 2, 3 input leakage current (any input) i il -1 +1 a output leakage current (any output) i ol -1 +1 a output logic 1 voltage (i out = -1.0 ma) v oh 2.4 1 output logic 0 voltage (i out = +2.1 ma) v ol 0.4 1 write protection voltage v pf 4.25 4.50 v 1 battery switch-over voltage v so v bat 1, 4
ds1742 6 of 12 dc electrical characteristics (over the operating range; v cc = 3.3v 10%) parameter symbol min typ max units notes active supply current i cc 10 30 ma 2, 3 ttl standby current ( ce = v ih ) i cc1 0.7 2 ma 2, 3 cmos standby current ( ce = v cc - 0.2v) i cc2 0.7 2 ma 2, 3 input leakage current (any input) i il -1 +1 a output leakage current (any output) i ol -1 +1 a output logic 1 voltage (i out = -1.0 ma) v oh 2.4 1 output logic 0 voltage (i out =2.1 ma) v ol 0.4 1 write protection voltage v pf 2.80 2.97 v 1 battery switch-over voltage v so v bat or v pf v 1, 4 read cycle, ac characteristics (over the operating range; v cc = 5.0v 10%) 70 ns access 100 ns access parameter symbol min max min max units notes read cycle time t rc 70 100 ns address access time t aa 70 100 ns ce to dq low-z t cel 55 ns ce access time t cea 70 100 ns ce data off time t cez 25 35 ns oe to dq low-z t oel 55 ns oe access time t oea 35 55 ns oe data off time t oez 25 35 ns output hold from address t oh 55 ns
ds1742 7 of 12 read cycle, ac characteristics (over the operating range; v cc = 3.3v 10%) 120 ns access 150 ns access parameter symbol min max min max units notes read cycle time t rc 120 150 ns 5 address access time t aa 120 150 ns 5 ce to dq low-z t cel 5 5 ns 5 ce access time t cea 120 150 ns 5 ce data off time t cez 40 50 ns 5 oe to dq low-z t oel 5 5 ns 5 oe access time t oea 100 130 ns 5 oe data off time t oez 35 35 ns 5 output hold from address t oh 5 5 ns 5 read cycle timing diagram
ds1742 8 of 12 write cycle, ac characteristics (over the operating range; v cc = 5.0v 10%) 70 ns access 100 ns access parameter symbol min max min max units notes write cycle time t wc 70 100 ns address access time t as 00 ns we pulse width t wew 50 70 ns ce pulse width t cew 60 75 ns data setup time t ds 30 40 ns data hold time t dh 00 ns address hold time t ah 55 ns we data off time t wez 25 35 ns write recovery time t wr 55 ns write cycle, ac characteristics (over the operating range; v cc = 3.3v 10%) 120 ns access 150 ns access parameter symbol min max min max units notes write cycle time t wc 120 150 ns address setup time t as 00 ns we pulse width t wew 100 130 ns ce pulse width t cew 110 140 ns data setup time t ds 80 90 ns data hold time t dh 00 ns address hold time t ah 00 ns we data off time t wez 40 50 ns write recovery time t wr 10 10 ns
ds1742 9 of 12 write cycle timing diagram, write enable controlled write cycle timing diagram, ce controlled power-up/down characteristics (over the operating range; v cc = 5.0v 10%) parameter symbol min typ max units notes ce or we at v ih , before power-down t pd 0s v cc fall time: v pf(max) to v pf(min) t f 300 s v cc fall time: v pf(min) to v so t fb 10 s v cc rise time: v pf(min) to v pf(max) t r 0s power-up recover time t rec 35 ms expected data retention time (oscillator on) t dr 10 years 5, 6
ds1742 10 of 12 power-up/down waveform timing 5-volt device power-up/down characteristic (over the operating range; v cc = 3.3v 10%) parameter symbol min typ max units notes ce or we at v ih , before power-down t pd 0 s v cc fall time: v pf(max) to v pf(min) t f 300 s v cc rise time: v pf(min) to v pf(max) t r 0 s power-up recovery time t rec 35 ms expected data retention time (oscillator on) t dr 10 years 5, 6 power-up/down waveform timing 3.3-volt device capacitance (t a = 25 c) parameter symbol min typ max units notes capacitance on all input pins c in 7pf capacitance on all output pins c o 10 pf
ds1742 11 of 12 ac test conditions output load: 100 pf + 1ttl gate input pulse levels: 0.0 to 3.0 volts timing measurement reference levels: input: 1.5v output: 1.5v input pulse rise and fall times: 5 ns notes: 1. voltage referenced to ground. 2. typical values are at 25 c and nominal supplies. 3. outputs are open. 4. battery switch-over occurs at the lower of either the battery voltage or v pf . 5. data retention time is at 25 c. 6. each ds1742 has a built-in switch that disconnects the lithium source until v cc is first applied by the user. the expected t dr is defined as a cumulative time in the absence of v cc starting from the time power is first applied by the user. 7. real time clock modules can be successfully processed through conventional wave-soldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85 c. post-solder cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used to prevent damage to the crystal.
ds1742 12 of 12 ds1742 24-pin package

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